? semiconductor components industries, llc, 2001 april, 2001 rev.1 1 publication order number: sr002an/d sr002an/d linear regulators with microprocessor control functions kieran o'malley on semiconductor 2000 south county trail east greenwich, ri 02818 although microprocessors are often considered the abrainso of a control system, they need a well regulated power supply and constant supervision for consistent operation. the system designer must choose between building these supervisory functions using discrete circuitry, a microprocessor supervisory ic, or a regulator which has the supervisory functions included. this article examines each of the common supervisory functions required in a microprocessor control system and shows how they are integrated into a smart regulator ? to provide a complete system solution. introduction on semiconductor smart regulators are linear regulators that provide a power supply and supervisory functions for microprocessor control systems. along with the basic 5.0 v or 3.3 v supply, a microprocessor also requires circuitry to provide functions such as: ? power on reset ? low voltage reset ? watchdog timer ? wakeup timer ? onoff control or enable several of the newer microprocessors have some of these functions already incorporated but most designers prefer that supervisory tasks are handled by an external device to provide an additional safety measure. (a microprocessor will not be able to detect its own errors, especially in low supply voltage situations.) microprocessor control functions can be implemented with individual discrete circuits, microprocessor supervisor ic's, or by using a smart regulator like those manufactured by on semiconductor . the advantage that a smart regulator offers is complete integration where all the functions are fully compatible with each other in a single space saving design. power on reset when power is initially applied to a microprocessor, its internal registers contain random data. applying a reset to the microprocessor overcomes the potential for errors by resetting all internal circuitry to a predictable starting point. to ensure proper startup, the reset input of the microprocessor must be held low for a fixed amount of time. during this time the supply voltage reaches its nominal value and the oscillator frequency stabilizes. this power on reset period is usually specified by the microprocessor manufacturer as a number of clock cycles or a time period. the time period ranges from 20 to several hundred milliseconds depending on the microprocessor. reset circuitry is powered either directly from the regulator's input voltage, v in or from its output voltage, v out . if the reset circuitry is powered from v in , the reset will not function when the input voltage disappears suddenly or drops out of regulation. however, the microprocessor may continue to work, powered by the output capacitor voltage. without a valid reset, the microprocessor may operate erroneously. because of this possibility, all on semiconductor smart regulator reset circuitry is powered from the regulator's output voltage, v out , rather than its input voltage, v in . reset will function for values of v out as low as 1.0 volt. delayed reset on semiconductor smart regulators have either a delayed reset or a real time reset. in a delayed reset circuit like the one in the cs8126, the user programs the time for which the reset output remains low with an external capacitor, c delay . the cs8126 uses an internal current source to charge c delay when the output voltage is above a predetermined level (v rt(on) ) as shown in figure 1. the reset output is an open collector npn transistor that requires a pull up resistor (figure 2, r rst ) connected to v out . the reset delay time is calculated from the formula: delaytime c delay v charge (delay threshold) i charge using an ideal 0.1 m f capacitor, the delay time ranges from 22 ms to 65 ms due to regulator variation alone. http://onsemi.com application note
sr002an/d http://onsemi.com 2 figure 1. reset waveforms: output voltage, reset voltage and delay capacitor voltage. t delay is the time between the capacitor's initial charging and the issuance of the reset signal l v out t delay v rt(on) reset v r c delay v rt(off) v rh v dh v dis v dc(hi) v dc(lo) (3) a point often overlooked by designers is that the capacitor tolerance must be taken into account in the equation to guarantee the required minimum delay time for the microprocessor. if the capacitor has a 10%, the delay could range from 19.5 ms to 71.5 ms. real time reset a real time reset circuit like the one in the cs8120 also consists of an open collector npn transistor. to provide a reset delay, the user can connect an rc network as shown in figure 2. figure 2. rc network for reset delay in the cs8120 v out r rst c rst 5.0 v to m p and system power c out reset to m p reset port cs8120 the capacitor c rst is charged to v out through the parallel combination of r rst and the input impedance of microprocessor reset line. unlike the delayed reset, the real time reset output rises gradually from 0 v when a delay capacitor is used. if no capacitor is used, reset goes high as soon as the output voltage is within specification. of the two types of reset circuitry, more precise control is offered by the delayed reset option. the reset delay time for the cs8120 is calculated using the standard capacitor charge formula: v e t rc solving for the rc time constant, the equation becomes: r tot c rst t delay ln v t v out v rst v out where: r tot = r rst in parallel with r in , r in = input impedance of the microprocessor, c rst = reset delay capacitor, t delay = desired delay time, v t = microprocessor logic threshold voltage, and v rst = vsat of the reset pin (~0.4 v) low voltage reset the power supply for a microprocessor must be constantly monitored to ensure that it is within specification. undervoltage conditions such as brief glitches or gradual decay due to an aging battery, can cause microprocessor errors. power on reset and low voltage reset usually use the same circuitry and issue a reset when the voltage they are monitoring falls out of regulation (figure 3). as v cc rises above its minimum operating value, the reset output remains low for a fixed period (t delay ).
sr002an/d http://onsemi.com 3 all on semiconductor reset circuitry includes hysteresis (v rh ) to provide noise immunity and avoid errors as the battery ages and the supply falls slowly out of regulation. figure 3. reset waveforms during a low voltage condition. when v out falls below v rton , the reset goes low and remains low for a fixed period, t delay after v out rises above v rt ( off ) 5.0 v 5.0 v 0 v 0 v v out v rt(on) reset v rt(off) t delay v rh watchdog in a typical microprocessor system, the software routines are usually written as a number of modules within a larger, continuous loop. an error can cause the program to stall within a module. a watchdog timer circuit is usually connected to the output port of a microprocessor and a short software routine is written to send an interrupt to this port within a predetermined time period. this short routine is incorporated in each module in the program loop. if the expected data is not received within this time period, the watchdog timer assumes there is an error and issues a system reset. several of the newer microprocessors have internal watchdog timers which are used to perform the self check described above. system designers who are reluctant to use the internal watchdog, implement it using either discrete circuitry, a specialized microprocessor supervisory ic or a smart regulator with a builtin watchdog timer such as the cs8140, cs8141 or cs8151 from on semiconductor. the cs8140 has an externally programmable watchdog window while the cs8141 has a programmable lower watchdog frequency. the cs8140 offers tighter control since it has an upper and lower frequency threshold but the software requirements are more stringent. figure 4 shows a typical timing diagram for the cs8140 where, after a period of normal operation, the watchdog signal frequency increases beyond the upper limit. a programmable reset pulse train is issued until a watchdog signal is received within the required time period. wake up microprocessors used in battery operated equipment usually have an operating mode where some or all of the internal circuitry is shut down to conserve energy. this low power operating mode is known by many different names including, halt, suspend, idle, sleep, etc., depending on the manufacturer. the microprocessor can be restarted from this sleep mode using a real time interrupt triggered by some external event or by periodically interrupting the microprocessor and having it perform a checking routine to see if it needs to remain active or return to the sleep mode. the cs8151 combines a linear regulator with watchdog, wakeup and reset control functions. the wakeup output signal interrupts the microprocessor periodically at a frequency determined by an external capacitor. in the cs8151, a single capacitor (c delay in figure 5) determines the wake up signal frequency, wake up delay time and reset pulse width. the smart regulator control functions are integrated in such a way that the regulator issues a wakeup signal and waits for a watchdog signal back from the microprocessor (figure 6). if the microprocessor fails to send a wdi within one wake up period, the regulator issues a reset (figure 7). fast wdi signal figure 4. wdi frequency rises above the upper frequency threshold after a normal period of operation. the cs8140 issues a reset pulse train until the wdi frequency falls back within its preset limits v in v enable wdi reset v out 0 v 0 v 0 v por normal operation batt
sr002an/d http://onsemi.com 4 figure 5. in the cs8151, c in is a filtering capacitor and c o is a compensation capacitor. c delay sets the timing for the reset and wake up functions v in gnd v out v c c in c delay wdi wake up reset c o i/o reset i/o cs8151 microprocessor battery c delay figure 6. power up, sleep mode and normal operation for cs8151. after power up, the microprocessor remains in sleep mode and sends back at least one wdi within each wake up period v in wake up reset v out por normal operation with varying watchdog signal wdi sleep mode wake up duty cycle = 50% power up reset high to wakeup delay time v in wake up reset v out por wdi wake up period reset delay time reset high to wakeup delay time reset high to wakeup delay time figure 7. when the microprocessor fails to send a wdi signal to the regulator, the cs8151 issues a reset back to the microprocessor until a wdi appears
sr002an/d http://onsemi.com 5 onoff control or enable the enable or on/off pin provides a means of controlling the regulator's output voltage (one or both outputs in a dual regulator). this feature is also called shutdown or inhibit depending on the manufacturer and the device. switching off outputs when they are not needed reduces power consumption and prolongs battery life. enable circuitry is usually ttl or cmos compatible so that it can be controlled directly from logic circuitry. if enable is not required in a design, it should be tied high or low depending on its signal polarity, to keep the output permanently on. with the cs8120 in figure 8, the output voltage is on when the voltage on the enable pin is less than 1.1 v. conversely, the cs8140's enable is active high. its enable pin must be tied high, to keep the output voltage on. figure 8. the cs8120 regulator output remains on when the enable voltage is low and is switched off when enable is pulled high v in v enable v out 5.0 v 5.0 v 5.0 v 0 v 0 v 0 v working with integrated smart features a design example when a number of microprocessor control features occur in a single smart regulator, it's not always clear which one(s) should be considered first. however, for most microprocessor based systems, the overriding requirement is the reset delay (also known as power on reset). for smart regulators like the cs8140 where reset, enable and watchdog are set by one external capacitor, the capacitor is chosen to meet the reset delay requirement. reset duration and watchdog timing follow. for the cs8140, reset delay is given by: t por (typical) (4.75 10 5 ) c delay from the cs8140 data sheet, the reset delay has a tolerance of 37%. in addition, the external capacitor has a 10% tolerance. the equation for the minimum t por is t por (min) (4.75 10 5 0.63) c delay 0.9 solving for the minimum value of c delay , c delay (min) t por (min) 2.69 10 5 if, for this design example, the reset delay period must be a minimum of 200 ms, then c delay (min) 0.743 f since the closest standard value is 0.82 m f, the minimum and maximum delays using 0.82 m f will be 220 ms and 586 ms respectively. the duration of the reset pulse in the cs8140 is given by: t wdi(reset) (1.0 10 4 ) c delay with the capacitor value fixed at 0.82 mf, and a tolerance of 50% due to the ic, and 10% due to the capacitor, the duration of the reset pulse ranges from 3.69 ms to 13.5 ms. the watchdog signal can be expressed as a frequency or time period. from a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second. the maximum and minimum watchdog times are given by: t wdi(lower) (1.3 10 5 )c delay t wdi(upper) (3.82 10 4 )c delay as with the above calculations, the tolerance of the ic and the external capacitor must be considered. with a tolerance of 20% from the ic and 10% from the capacitor, the above two equations become t wdi(lower) (1.30 1.2 10 5 )(1.1 0.82 10 6 ) 141 ms t wdi(upper) (3.82 0.8 10 4 )(0.9 0.82 10 6 ) 22.5 ms t wdi(lower) (1.30 0.8 10 5 )(0.9 0.82 10 6 ) 76 ms t wdi(upper) (3.82 1.2 10 4 )(1.1 0.82 10 6 ) 41 ms figure 9. wdi signal for c delay = 0.82 f using cs8140 fail hz ms c = 0.1 m f 10% 7 fail pass 913 24 3244 141 107 76 41 31 22.5 based on these calculations, the software must be written so that a watchdog signal arrives at least every 76 ms but not faster than every 41 ms. energy conservation and smart features energy conservation is another benefit of using a regulator with integrated microprocessor control features. using the cs8140 or cs8141 as indicated in figure 10, the microprocessor can control its own power down sequence.
sr002an/d http://onsemi.com 6 the momentary contact switch quickly charges c1 through r1. when the voltage across c1 reaches 3.95 v ( the enable threshold), the output switches on and v out rises to 5.0 v. after a delay period determined by c delay , a frequency programmable reset pulse train is generated at the reset output. the pulse train continues until the correct watchdog signal appears at the wdi pin. c1 is now left to discharge through the input impedance of the enable pin (approximately 150 k w ) and the enable signal disappears. the output voltage remains at 5.0 v as long as the cs8140 continues to receive the correct watchdog signal. figure 10. applications diagram for cs8140 provides a 5.0 v tightly regulated supply and control function to the microprocessor. in this application, the microprocessor controls its own power down sequence ( see text ) v in v out v cc switch r1 110 k 2.7 k 9.0 v c 2 0.1 m f reset wdi gnd c delay enable 10 m f reset watchdog port microprocessor cs8140/1 c 1 0.1 m f the microprocessor can power itself down by terminating its watchdog signal. when the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. in response, the regulator generates a reset signal and goes into a sleep mode where v out drops to 0 v, shutting down the microprocessor. conclusion as the cs8140 design example illustrates, smart regulators with their integrated microprocessor control feature offer a level of control and flexibility unavailable with discrete implementations.
sr002an/d http://onsemi.com 7 notes
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